1. Field of the Invention
The present invention relates to a debugging mechanism for a processor.
2. Description of the Related Art
The increase in the degree of integration and complexity in the logic of processors has been remarkable in recent years, causing the work time for debugging to be continually increased. In a debugging of an arithmetic unit of a processor carried out Out-of-Order, it is important to know information (i.e., the history of arithmetic operations) indicating how and in what sequence each arithmetic unit has performed execution, thus requiring a configuration for recording and reading the information. Currently, a method widely used as one method for a debugging is to add a scan circuit to a latch incorporated in a processor and read the latch information. As a specific example, there is a known method to add a scan circuit to a latch incorporated in, for example, a JTAG (Joint Test Action Group)-compliant processor and to read the information from the latch.
As a related art, there is a debugging mechanism employing a plurality of latches each equipped with a scan circuit and each recording the arithmetic operation information while shifting the information, thereby retaining the arithmetic operation execution information within the processor at a plurality of timings. The debugging mechanism according to the related art records the content of the arithmetic operation execution and the timing of the arithmetic operation execution of each arithmetic unit. That is, the related art provides a counter and records the counter value and the signal of a recording target (i.e., arithmetic operation data). This configuration enables a person performing debugging or someone else to know what arithmetic operation has been executed and in what sequence each of the arithmetic units has performed execution, just by scanning the recorded data. It has not been possible to know, however, the execution intervals (i.e., cycle intervals) between the individual arithmetic operations of each arithmetic unit, or to know the relative execution order of a plurality of arithmetic units (i.e., in some cases judging them clearly is not possible).
FIG. 12 exemplifies the configuration of a debugging mechanism according to the related art described above.
The debugging mechanism 100 shown in FIG. 12 comprises a counter 101, and individual storage units 110, 120 and 130, corresponding to the respective arithmetic units. It is assumed here that there are three arithmetic units (assuming the arithmetic units X, Y and Z, although none of them is shown in a drawing herein). The arithmetic unit X executes a prescribed arithmetic operation on the basis of the signal of recording target (noted as “record target signal” hereinafter) A (i.e., arithmetic-operation-use input data) when control signal V_A, which is a startup control signal (VALID), turns to valid (“1”). Likewise, a record target signal B and a control signal V_B are input into the arithmetic unit Y, and a record target signal C and a control signal V_C are input into the arithmetic unit Z.
Further, since it is assumed here that the counter 101 is a 3-bit counter, a 3-bit count value is output from the COUNT terminal of the counter 101. Taking a storage unit 110 corresponding to the arithmetic unit X as an example, the storage unit 110 comprises a shift register 111, which receives a record target signal A as an input, and when the control signal V_A is “1”, stores the record target signal A and shifts it by one; and a shift register 112, which receives the count value as input, and when the control signal V_A is “1”, stores the count value and shifts it by one. The other storage units 120 and 130 are likewise configured, and they are different only in the sense that the input and stored data and the control signal are the record target signal B and the control signal V_B, and the input and stored data and the control signal are the record target signal C and the control signal V_C.
Each shift register of each storage unit has the same configuration, and the only exception is that input data are different, and therefore the description here is provided by exemplifying the shift register 111. The shift register 111 is constituted by six registers, i.e., registers A1, A2, A3, . . . , A6, in which a discretionary record target signal A externally input into the debugging mechanism 100 is first stored in the register A1 then is shifted to the register A2 when the next record target signal A is stored in the register A1, and it is shifted to the registers A3, A4, A5 and A6 in this order and is eventually shifted out. The control signal V_A is also input into the shift register 112, so that, at every time the control signal V_A turns to “1”, the present count value of the counter 101 is stored in the shift register 112 anew and the count value already stored in each register of the shift register 112 is shifted to the immediate next registers.
Then, the data stored in each of the shift registers 111 through 132 is externally read (scanned) at a discretionary timing. For example, when it is assumed that the values and the timings of the record target signals A through C and the control signals V_A through V_C are as shown in FIGS. 13A through 13C, the data scanned from the shift registers 111 through 132 are as shown in FIGS. 14A through 14C. That is, each of the storage units 110 through 130 has records of the record target signal and the counter value when the control signal is “1”.
Here, the counter 101 is a 3-bit counter, as described above, and therefore the counter counts up sequentially, i.e., 000, 001, 010 and so on, resets the count value when it reaches 111 and then again counts up in the sequence 000, 001, 010 and so on (which is called a cyclic counting). The storage units 110, 120 and 130 each store, and shift, the input record target signal A and the count value only when the input control signal to the unit is “1”. Therefore, for example, the storage unit 110 stores/shifts the record target signal A and the count value only when the count values are 010, 101, 000, 010, 011 and 111 (refer to FIG. 13A), and therefore the storage content of the storage unit 110 which is read out by scanning afterwards is as shown in FIG. 14A.
Note that a clock CLK input to the counter 101 is an internal clock of the processor and that the individual arithmetic units X through Z are also controlled in accordance with the clock CLK, and therefore the counter 101 will operate synchronously with these arithmetic operations. Further note that, referring to FIGS. 14A through 14C, each piece of data shown leftmost (noted as “leftmost data” hereinafter) in the figure represents data stored in the register shown on the rightmost side (i.e., the register A6 in the case of the shift register 111) from among the individual shift registers shown in FIG. 12. That is, the leftmost data represents the oldest piece of data from among the recorded data. The pieces of data shown on the rightmost side in the figure as shown in FIGS. 14A through 14C are the newest pieces of storage information (i.e., the data stored in register A1 in the case of the shift register 111). The number of memory elements of each shift register shown in FIG. 12 is six, and therefore the data in the record target signal A=“1” and the count value=“010” shown, as an example, in FIG. 14A will be shifted out when a further piece of data is recorded anew.
Here, assume that the person performing debugging considers the operating order of each arithmetic unit on the basis of data read (scanned) from the storage units 110, 120 and 130, as with actual debugging. FIGS. 15A through 15C show the operating order of each arithmetic unit, which may be able to be judged from the storage content shown in FIGS. 14A through 14C. Note that each of FIGS. 15A through 15C shows the values of record target signals newly recorded at the time at which a new piece of data is recorded in each shift register.
Since the actual operating orders are as shown in FIGS. 13A through 13C, FIG. 15A indicates a correct judgment result. From the storage contents shown in FIGS. 14A through 14C, however, a judgment as shown in FIG. 15B or 15C can be made and therefore the person performing debugging cannot know which judgment result is correct.
The reason why such a situation is brought about is that the counter 101 is cyclically operated as described above. As an example, even if the count value=“101” is recorded, sometimes it cannot be judged to which cycle the count value=“101” belongs. Of course, it is possible to make a judgment in some cases. In the example shown here, the record target signal A can be clearly judged, and the same judgment result is indicated for all of FIGS. 15A through 15C. This is because the first count value=“000” in the second cycle is recorded by chance in the case of the record target signal A, and this enables the judgment that the previous record data is the first cycle and the following record data is the second cycle to be made. However, this is based on the fact that the counter 101 is operated only for the second cycle, and therefore, if it is operated for the third cycle and thereafter, the judgment will be disabled (This is because, for example, no data is recorded in the second cycle in some cases, and all pieces of record data following the count value “000” might be the data recorded in the third cycle).
As for the case of the record target signals B and C, even if it is premised that the counter 101 is operated only until the second cycle, there are plural possible patterns as exemplified in FIGS. 15A through 15C, and hence it cannot be judged which of these is correct. Taking the record target signal B as an example, only the data of the count value=“111” stored last is the data of the second cycle and all other pieces of data are ones recorded in the first cycle, and this is correctly shown in FIG. 15A. However, there are possibilities that all pieces of data are of the second cycle as shown in FIG. 15B and that all pieces of data are of the first cycle as shown in FIG. 15C (and in addition, other patterns are also possible).
Objects of the present invention, related to a debugging mechanism retaining the arithmetic operation execution information pertaining to a processor, are to provide a debugging mechanism for recording an operation history of each arithmetic unit so as to judge clearly the execution sequence and the cycle interval for each arithmetic unit or so as to judge clearly a relative execution order of a plurality of arithmetic units, and to provide an arithmetic operation unit, a processor and the like, which comprise the debugging mechanism.